LECTURE NOTES AND REFERENCES

 

Lecture 1

Lecture Note

 

Lecture 1

Lecture Note.

 

Lecture 1

Lecture Note.

 

Lecture 1

Lecture Note.

 

Lecture 1

Lecture Note.

References:

  1. A. E. Ruehli, “Inductance calculations in a complex integrated circuit environment,” IBM J. Res. Develop., pp. 470–481, Sept. 1972. [PDF]

  2. A. Deutsch, et al., “When are transmission-line effects important for on-chip interconnections?,” IEEE Trans. Microwave Theory Tech., vol. 45, pp. 1836–1846, Oct. 1997. [PDF]

Lecture 1

Lecture Note.

 

Lecture 1

Lecture Note.

 

Lecture 1

Lecture Note.

References:

  1. H. F. Dadgour, R. V. Joshi and K. Banerjee , "A Novel Variation-Aware Low-Power Keeper Architecture for Wide Fan-in Dynamic Gates," ACM Design Automation Conference (DAC), San Francisco, California, July 24-28, 2006, pp. 977-982. [PDF]  

Lecture 1

Lecture Note.

References:

  1. P. Yang, B. Epler and P. Chatterjee, "An Investigation of the Charge Conservation Problem for MOSFET Circuit Simulation," IEEE journal of Solid State Circuits, Vol. 18, No. 1, pp. 128-138, Feb. 1983. [PDF]  

Lecture 1

Lecture Note.

References:

  1. T. Sakurai and A R. Newton, "Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas," IEEE d. of Solid State Circuits, Vol. 25, No. 2, pp. 584-594, Apr. 1990. [PDF]  

  2. S. Thompson, P. Packan, and M. Bohr, “MOS scaling: Transistor challenges for the 21st century,” Intel Technol. J., vol. Q3, 1998. [PDF]  

  3. Sheng-Chih Lin and Kaustav Banerjee, "Cool Chips: Opportunities and Implications for Power and Thermal Management" IEEE Transactions on Electron Devices, Vol. 55, No. 1, pp. 245-255, 2008. [PDF]  

  4. D. B. Scott, W. R. Hunter, H. A. Shichijo, "Transmission Line Model for Silicided Diffusions: Impact on the Performance of VLSI Circuits," IEEE Journal of  Solid-State Circuits, Vol. 17, Issue 2, pp. 281 - 291, 1982.  [PDF]  

Lecture 1

Lecture Note.

References:

  1. S. Borkar, "Design challenges of technology scaling," IEEE Micro, vol. 19, 1999 [PDF]  

  2. K. Banerjee and A. Mehrotra, "A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs," IEEE Transactions on Electron Devices, Vol. 49, No. 11, pp. 2001-2007, 2002. [PDF]    

  3. A. P. Chandrakasan and R. W. Brodersen, “Minimizing power consumption in digital CMOS circuits,” Proc. IEEE, vol. 83, no. 4, pp. 498–523, Apr. 1995. [PDF]

  4. R. Gonzalez, B. M. Gordon, and M. A. Horowitz, “Supply and threshold voltage scaling for low power CMOS,” IEEE J. Solid-State Circuits, vol.
    32, no. 8, pp. 1210–1216, Aug. 1997.
     [PDF]

  5. S-C. Lin and K. Banerjee, “A Design-Specific and Thermally-Aware Methodology for Trading-off Power and Performance in Leakage-Dominant
    CMOS Technologies,” IEEE Transactions on Very Large Scale Integration Systems, Vol. 16, No. 11, pp. 1488-1498, Nov. 2008. [PDF]

 

Lecture 1

Lecture Note.

References:

  1. S.H. Gunther et al., “Managing the Impact of Increasing Microprocessor Power Consumption,” Intel Technology Journal 1st quarter,
    2001.
     [PDF]  

  2. R. Viswanath et al., “Thermal Performance Challenges from Silicon to Systems,” Intel Technology Journal 3rd quarter, 2000.  [PDF]    

  3. Sheng-Chih Lin, Greg Chrysler, Ravi Mahajan, Vivek De and Kaustav Banerjee, "A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part I: Electrothermal Couplings and Full-Chip Package Thermal Model," IEEE Transactions on Electron Devices, Vol. 54, No. 12, pp. 3342-3350, 2007. [PDF]  

  4. Sheng-Chih Lin, Greg Chrysler, Ravi Mahajan, Vivek De and Kaustav Banerjee, "A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part II: Electrothermal Couplings and Full-Chip Package Thermal Model," IEEE Transactions on Electron Devices, Vol. 54, No. 12, pp. 3351-3360, 2007.  [PDF]  

Lecture 1

Lecture Note.

Lecture 14

Lecture Note.

 

Lecture 15

Lecture Note.

References:

  1. E.G. Friedman, "Clock distribution networks in synchronous digital integrated circuits," Proc. IEEE, vol.89, no.5, pp.665–692, May 2001. [PDF]  

 

Lecture 15

Lecture Note.

References:

  1. K. Banerjee, S. J. Souri, P. Kapur, and K. C. Saraswat, Eds., “3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration,” Proc. IEEE 89, No. 5, 602–633 (2001).[PDF]  

 

Lecture 15

Lecture Note.

References:

  1. R. W. Mann et al. , "Ultralow-power SRAM technology," IBM J. RES. & DEV. VOL. 47 NO. 5/6 SEPTEMBER/NOVEMBER 2003. [PDF]  

 

Lecture 15

Lecture Note.

References:

  1. J. A. Mandelman et al. , "Challenges and future directions for the scaling of dynamic random-access memory (DRAM)," IBM J. RES. & DEV. VOL. 46 NO. 2/3 MARCH/MAY 2002.  [PDF]

 

 

 

 

 

 

 

 

Back to Course Homepage