LECTURE NOTES AND REFERENCES

Week 1

1. S. Borkar, "Design challenges of technology scaling," IEEE Micro, vol. 19, 1999 [PDF]
2. S. Borkar, et al., " Parameter Variations and Impact on Circuits and Microarchitecture," DAC, 2003, pp. 338-342. [PDF]

Week 2

Lecture 3

1. D. Radhakrishnan, et al., "Formal Design Procedures for Pass Transitor Switching Circuits," IEEE JSSC, 1985 [PDF]
2. N.F. Goncalves, et al., " NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Strurcures ," IEEE JSSC, 1983. [PDF]
3. V. De and S. Borkar, " Technology and Design Challenges for Low Power and High Performance," LPED, 1999. [PDF]

Week 3

1. Hybrid NEMS-CMOS Integrated Circuits: A Novel Strategy for Energy -Efficient Designs [PDF]
Hamed F. Dadgour and K. Banerjee
IET Transactions on Computers and Digital Techniques—Special Issue on Advances in Nanoelectronics Circuits and Systems, Vol. 3, No. 6,
pp. 593-608, Nov. 2009.

2. Scaling and Variability Analysis of CNT-Based NEMS Devices and Circuits with Implications for Process Design [PDF]
H. Dadgour, A. M. Cassell and K. Banerjee
IEEE International Electron Devices Meeting (IEDM), pp. 529-532, San Francisco, Dec. 15-17, 2008.

Week 4

1. Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas [PDF]
Takayasu Sakurai and A. Richard Newton
IEEE Journal of Solid State Circuits, Vol. 25, No. 2, pp. 584-594, April 1990.

2. MOS Scaling: Transistor Challenge for the 21st Century [PDF]
Scott Thompson, Paul Packan, and Mark Bohr
Intel Technology Journal 1998.

3. Dual Work Function Metal Gate CMOS Transistors by Ni-Ti Interdiffusion [PDF]
Igor Polishchuk, Pushkar Ranade, Tsu-Jae King, and Chenming Hu
IEEE Electron Device Letters, Vol. 23, No. 4, pp. 200-202, April 2002.

4. A Computational Study of Thin-Body, Double-Gate, Schottky Barrier MOSFETs [PDF]
Jing Guo and Mark S. Lundstrom
IEEE Transactions on Electron Devices, Vol. 49, No. 11, pp. 1897-1902, November 2002.

5. Sub-50nm P-Channel FinFET [PDF]
X. Huang, W.-C. Lee, Charles Kuo, D. Hisamoto, Leland Chang, J. Kedzierski, E. Andersion, H. Takeuchi, Y.-K. Choi, K. Asano,
V. Subramanian, T.-J. King, J. Bokor, and C. Hu
IEEE Transactions on Electron Devices, Vol. 48, No. 5, pp. 880-886, May 2001.

6. Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits [PDF]
Yasin Khatami, and Kaustav Banerjee
IEEE Transactions on Electron Devices, Vol. 56, No. 11, pp. 2752-2761, November 2009.

Week 5

1. A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs--Part I: Electrothermal Couplings
and Full-Chip Package Thermal Model [PDF]
Sheng-Chih Lin, Greg Chrysler, Ravi Mahajan, Vivek K. De, and Kaustav Banerjee
IEEE Transactions on Electron Devices, Vol. 54, No. 12, pp. 3342-3350, December 2007.

2. A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs--Part II: Implementation and
Implications for Power Estimation and Thermal Management [PDF]
Sheng-Chih Lin, Greg Chrysler, Ravi Mahajan, Vivek K. De, and Kaustav Banerjee
IEEE Transactions on Electron Devices, Vol. 54, No. 12, pp. 3351-3360, December 2007.

3. Cool Chips: Opportunities and Implications for Power and Thermal Management [PDF]
Sheng-Chih Lin and Kaustav Banerjee
IEEE Transactions on Electron Devices, Vol. 55, No. 1, pp. 245-254, January 2008.

4. A Design-Specific and Thermal-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant
CMOS Technologies[PDF]
Sheng-Chih Lin and Kaustav Banerjee
IEEE Transactions on Electron Devices, Vol. 16, No. 11, pp. 1488-1498, November 2008.

Week 6

1. A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs [PDF]
  Kaustav Banerjee, and Amit Mehrotra
IEEE Transactions on Electron Devices, Vol. 49, No. 11, pp. 1488-1498, November 2002.

2. Analysis of On-Chip Inductance Effects for Distributed RLC Interconnects [PDF]
  Kaustav Banerjee, and Amit Mehrotra
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 21, No. 8, pp. 904-915, August 2002.

3. Global [Interconnect] Warming [PDF]
  Kaustav Banerjee, and Amit Mehrotra
IEEE Circuits & Devices Magazine, pp. 16-32, September 2001.

4. Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI [PDF]
A. H. Ajami, Kaustav Banerjee, and M. Pedram
Analog Integrated Circuits and Signal Processing, Springer Science, pp. 277-290, 2005.

5. Modeling and Extraction of Nanometer Scale Interconnects: Challenges and Opportunities (Invited) [PDF]
R. Suaya, R. Escovar, S. Ortiz, Kaustav Banerjee, and N. Srivastava
Proceeding of the 23rd Advanced Metallization Conference (AMC), San Diego, October 16-19, 2006.

6. Modeling and Analysis of Nonuniform Substrate Temperature Effects on Global ULSI Interconnects [PDF]
A. H. Ajami, Kaustav Banerjee, and M. Pedram
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 24, No. 6, pp. 849-861, June 2005.

7. Interconnect Modeling and Analysis in the Nanometer Era: Cu and Beyond [PDF]
Kaustav Banerjee, S. Im, and N. Srivastava
Proceeding of the 22nd Advanced Metallization Conference (AMC), Colorado Springs, CO, September 27-29, 2005.

Week 7

1. A Probabilistic Framework for Power-Optimal Repeater Insertion in Global Interconnects Under Parameter Variations [PDF]
Vineet Wason and Kaustav Banerjee
International Symposium on Low Power Electronic Design (ISLPED), pp. 131-136, San Diego, CA, August 8-10, 2005

2. A Statistical Framework for Estimation of Full-Chip Leakage-Power Distribution Under Parameter Variations [PDF]
H. F. Dadgour, Sheng-Chih Lin, and Kaustav Banerjee
IEEE Transactions on Electron Devices, Vol. 54, No. 11, pp. 2930-2945, November 2007.

3. Analytical Expressions for High-Frequency VLSI Interconnect Impedance Extraction in the Presence of a
Multilayer Conductive Substrate [PDF]
N. Srivastava, Roberto Suaya, and Kaustav Banerjee
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 28, No. 7, pp. 1047-1060, July 2009.

Week 8

1. Clock Distribution Networks in Synchronous Digital Integrated Circuits [PDF]
Eby G. Friedman
Proceedings of the IEEE, Vol. 89, No. 5, pp. 665-692, May 2001.

2. NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Structures [PDF]
N. F. Goncalves and Hugo J. De Man
IEEE Journal of Solid-State Circuits, Vol. SC-18, No. 3, pp. 261-266, June 1983.

3. High-Speed CMOS Circuit Technique [PDF]
Jiren Yuan and Christer Svensson
IEEE Journal of Solid-State Circuits, Vol. 24, No. 1, pp. 62-70, Feb. 1989.

4. Impact of Die-to-Die and Within-Die Parameter Fluctuations on the Maximum Clock Frequency Distribution
for Gigascale Integration [PDF]
K. A. Bowman, Steven G. Duvall, and James D. Meindl
IEEE Journal of Solid-State Circuits, Vol. 37, No. 2, pp. 183-190, Feb. 1989.

Week 9

1. Ultralow-power SRAM Technology [PDF]
R.W. Mann et al.
IBM J. RES. & DEV., Vol. 47, No. 5/6, pp. 553-566, Sep./Nov. 2003.

2. Challenges and future directions for the scaling of dynamic random-access memory (DRAM) [PDF]
J. A. Mandelman, R. H. Dennard, G. B. Bronner, J. K. Debrosse, R. Divakaruni, Y. Li, and C. J. Radens
IBM J. RES. & DEV., Vol. 46, No. 2/3, pp. 187-212, Mar./May 2002.

Back to Course Homepage