Department of Electrical and Computer
Engineering
Digital Design Principles
ECE 152A - Fall
2004
Prof. Volkan Rodoplu
Lectures: Tuesday/Thursday
Office hours: Room 4113, Engineering I; Tuesday
Midterm Exam: October 21 from
(Girvetz Hall is between South Hall and the Library.)
Final Exam: December 9 from
Announcements
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(1) Submit the hardcopy part
to Prof. Rodoplu during his office hours on Nov.
23, 2:00-3:00 PM. If you cannot make it to my office hours, then leave your
portfolio with Lisa Dahlen in the WordPro office
(4th floor, Engineering I) by (2) Submit the softcopy part
by email to your lab TA's submission account. The IT people are working on
the email addresses for submission. There were problems earlier on Nov. 23
with these email submission accounts. If you got a bounce earlier, please
submit it again. You can submit the softcopy
part by email any time this week (until Friday, Nov. 26, ece152a_TA1@ece.ucsb.edu (for Vishal) ece152a_TA2@ece.ucsb.edu (for James) ece152a_TA3@ece.ucsb.edu (for Nilesh) ece152a_TA4@ece.ucsb.edu (for Aida) 11/17/04: HW# 3 solution has been
updated. 11/15/04: The deadline for
HW#5 has been postponed to 11/30/04. 11/15/04: Prof. Rodoplu will have no office hours on Tuesday 11/16/04 due
to a Ph.D. Qualifying Exam he has to chair. 11/10/04: An updated version
of template.v is available here on the web
page which includes several bug fixes. If you have problems compiling your
Verilog code, try downloading the newer version. 11/10/04: For Problem 20 on
HW#4: Assume that the other input to the XOR gate is simply one of the inputs
of the finite state machine. Which particular input it is does not affect the
answer. 10/27/04: The student
portfolio is due in Prof. Rodoplu's office in the
week of Nov. 25. The portfolio has the following components: 1)
Lab 5 Report, 2) 1 sample lecture note (photocopy), 3) 1 sample homework
(photocopy), 4) Lab 4 Verilog code (print out), 5) Digital image of Lab 4 or
Lab 5 final circuit (the file must be labeled clearly as Lab<4 or
5>_<lastname1>_<lastname2>, where the last names are the last
names of the students in that team. [Submitting one digital image per team is
fine.] You may submit additional items, but place the required items first in
your portfolio. 10/25/04: Solutions for
midterm exam have been posted under the “Solutions” section. 10/24/04: HW#3: New sections have been added to Problems 22, 23, and 24 in the course reader. These additional sections require you to write Verilog. Please use this updated version for HW#3. (updated as of 5:40 PM).
10/19/04: HW#1 Grading: The problem 3 is not considered towards the final grads of the HW#1 so the maximum points anybody can get on HW#1 will be 126 instead of 140. Please also disregard the grading of problem# 3 because you may have done it right, but is marked wrong. The problem was that the problem did not specify exactly what the bits A, B, C, D, E corresponded to, so there were more than 1 interpretation. For the most common interpretation, see the solutions of Problem #3 in HW#1 posted under "Solutions" on this web page. 10/17/04: Lab # 2
Troubleshooting ModelSim document is up on the web
(see below in the lab handouts section). 10/16/04: Lab # 3 handout
was again updated 11 AM on 10/16/04. Make sure to use this revised version. 10/15/04: Lab # 3 handout
was updated 2 PM on 10/15/04. Make sure to use this revised version! 10/14/04: Prof. Rodoplu's office hours on Thursday moved from 11:00 -
12:00 PM to 2:00 - 3:00 PM (effective 10/14/04). 10/13/04: James Tandon will have extra TA office hours on 10/14/2004 at
6:30-8:30pm to help with software issues on Lab #2. 10/11/04: Find the document
which you can use to find library paths for importing libraries into
Modelsim, under the section of Lab Handouts. 10/08/04: HW # 2 handout
and Course Reader were updated to their final version 9:00 AM on 10/08/04.
(There were changes to HW#2 Problems 10-17.) HW#2's deadline has also been
postponed. See below. 10/06/04: Prof. Rodoplu's office hours have changed. See the new office
hours above (effective 10/07/04). 10/06/04: Lab # 2 handout
was updated 10:30 PM on 10/06/04. Make sure to use this revised version! 10/05/04: Please use TTL
(7400 series) for your labs (not CMOS 4000 series parts!). 10/04/04: The step3 of
Lab#1 is taken out. Please carefully build your TTL design from the logic
circuit you obtained from the K-maps, so that your TTL design is logically
correct. 10/03/04: See the Midterm
Location above! It will be during class time but in a different location! 10/01/04: For the lab problem
sets, you need to hand in only 1 solution per team (put both team members'
names on your solutions.) 09/27/04: Check in the ECE Shop (Room: 1160, Engineering-I; M-F: 8:00-12:00 and 1:00-4:00) to get the access cards for the Digital lab. |
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(Updated on a weekly basis. Homework is
assigned from the reader.)
CourseReader_Problems 10 to 14
Homework
- Solutions
The TA's listed below each homework are the ones most knowledgeable about
that homework.
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HW
# 1 (due TA's: Vishal and Nilesh |
HW
# 2 (due TA's: James and Aida |
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HW
# 3 (due 5th floor, Engineering I Building) TA's: Vishal and Nilesh |
HW # 4
(due 5th floor, Engineering I
Building) TA's: Aida and
James |
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HW # 5
(due 5th floor, Engineering I Building) TA's: Nilesh and Vishal |
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Lab Handouts
Lab Schedule
Print out Data
Sheets for each lab
Import
libraries into Modelsim
ECE
Shop: List of Available Parts
Lab Sections
Engr I, Room 1124 (DigiLab)
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Monday 10 AM - 12:50 PM |
Monday 2:00 PM - 4:50 PM |
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Tuesday 7:00 PM - 9:50 PM |
Wednesday 8:00 AM - 10:50 AM |
Review Sessions
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Date |
Time & Place |
TA |
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Sep 27, 2004,
Monday,
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7 - 8 PM, Broida 1640 |
James |
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October 4, 2004, Monday |
7 - 8 PM, Broida 1640 |
James |
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**October 8, 2004, Friday**
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10 AM - 11 AM, Phelps 1260 |
Aida |
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October 18, 2004, Monday |
7 - 8 PM, Broida 1640 |
Vishal |
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October 25, 2004, Monday |
7 - 8 PM, Broida 1640 |
Nilesh |
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November 1, 2004, Monday |
7 - 8 PM, Broida 1640 |
Aida |
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November 8, 2004, Monday |
7 - 8 PM, Broida 1640 |
Vishal |
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November 15, 2004, Monday |
7 - 8 PM, Broida 1640 |
James |
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November 22, 2004, Monday |
7 - 8 PM, Broida 1640 |
Nilesh |
TA Office Hours
Engr I, Room 1124 (DigiLab)
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Aida Todri Friday 10 AM - 12 PM |
Nilesh Modi Monday
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James Tandon Wednesday 10 AM - 12 PM
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Vishal Mehta Thursday 10 AM - 12 PM |