`timescale 1ns/1ns


// This testbench performs a reset and then turns on the left turn signal
// It is up to the student to test additional cases and transitions
module test_bench;

reg CLK, RST, LEFT, RIGHT, BRAKE, HAZARD, LIGHTS;
wire [5:0] LEDS;

initial 
begin	
  #0 CLK <= 1'b0;
  #0 RST <= 1'b1;
 
 #0 LEFT <= 1'b0;
 #0 RIGHT <= 1'b0;
 #0 BRAKE <= 1'b0;
 #0 HAZARD <= 1'b0;
 #0 LIGHTS <= 1'b0;

#20 RST <= 1'b0;

#25 LEFT <= 1'b1;

 end
 
 always #10 CLK <= ~CLK;
 
 

main main01(CLK,RST,LEFT,RIGHT,BRAKE,HAZARD,LIGHTS,LEDS);


endmodule