LATCH DISCUSSION:

If you provide valid inputs to a level-sensitive latch (i.e. inputs that are assured to be stable a set-up time before the clock falls), the propagation delay through the latch should be measured from the point a set-up time before the clock falls. The reason is that the set-up time assures that the clock's falling does not mess up the output of the latch. The propagation time of a latch measures the worst-case delay from an input change of the latch to the
attainment of the correct output, while the clock is high. But once the set-up time requirement has been met, when the clock falls, at least part of the propagation through the latch has already occurred. So, it would be
wrong to account for another propagation delay (see how it is defined above) after the clock falls. The best way to understand this is to draw a clocked D-latch made up of cross-coupled NOR gates. Assume for simplicity
that each gate delay is 1 unit. Then, first work out what the set-up time is for this latch. Then, verify my statement above about from which point the propagation delay should be measured in this case.

Now, to turn to flip-flops: The main difference is that the propagation delay for the flip-flop is dominated NOT by the propagation delay from D-to-Q (i.e. D input change to output change) but rather from CLK-to-Q
(i.e. clock falling (for a negative-edge-triggered flip-flop) to the output's becoming valid.) To convince yourself, draw a flip-flop implementation that uses two cascaded D-latches (and an inverted clock to the second latch). The first latch is a level-sensitive D-latch that passes the input when the clock is HIGH. The second latch is a
level-sensitive D-latch that passes the input when the clock is LOW. Then, the set-up time for the flip-flop will be equal to the set-up time of the first latch. Assuming that this set-up time requirement has been met, you will need [propagation delay through first latch minus set-up time of first latch] seconds after the clock falls, to complete the propagation through the first latch. After a delay through the inverter (note that the clock goes through an inverter), the clock signal at the second D-latch falls (and this latch becomes enabled). Then, you need the clock-to-q delay to get a valid output at the second latch. The propagation delay through the first latch minus the set-up time of the first latch is usually small. So, the input signal is (almost) ready and waiting at the input to the second latch when the clock signal arrives. Hence, the propagation delay through the flip-flop is dominated by the clock-to-q time of the second latch. This is the reason that in calculating the minimum clock period, you need to add the propagation delay of the flip-flop (which is dominated by clock-to-q of the second latch) to the set-up time of the flip-flop.

In summary, the key is that the propagation delay through a latch and a flip-flop refer to different quantities: The propagation delay through the D-latch is the D-to-Q delay, whereas the propagation delay through the flip-flop is mostly CLK-to-Q delay.