January 16
Lecture Note : Lecture 1
References :
G.E. Moore - "Cramming more Components onto Integrated Circuits"
P.P. Gelsinger - "Microprocessors for the New Millennium: Challenges, Opportunities, and New Frontiers"
S. Borkar - "Design Challenges of Technology Scaling"
V. De and S. Borkar - "Technology and Design Challenges for Low Power and High Performance"
S. Borkar et al. - "Parameter Variations and Impact on Circuits and Microarchitecture"
January 18
Final project topics discussion
January 23
Lecture Note : Lecture 3
References :
Ivan Sutherland et al. - "Logical Effort: Designing Fast CMOS Circuits, Morgan Kaufmann", (Book from Amazon)
D. Radhakrishnan et al. - "Formal Design Procedures for Pass Transistor Switching Circuits"
N.F. Goncalves and H. De Man - "NORA: A Racefree Dynamic CMOS Technique for Pipelined Logic Structures"
H.F. Dadgour et al. - "A Novel Variation-Aware Low-Power Keeper Architecture for Wide Fan-in Dynamic Gates"
January 25
Lecture Note : Lecture 4
References :
K. Banerjee and A. Mehrotra - "Global (Interconnect) Warming"
K. Banerjee and A. Mehrotra - "A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs"
January 30
Lecture Note : Lecture 5
References :
K. Banerjee and A. Mehrotra - "Analysis of On-Chip Inductance Effects for Distributed RLC Interconnects"
A.H. Ajami et al. - "Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI"
V. Wason and K. Banerjee - "A Probabilistic Framework for Power-Optimal Repeater Insertion for Global Interconnects Under Parameter Variations"
A.H. Ajami et al. - "Modeling and Analysis of Non-Uniform Substrate Temperature Effects on Global ULSI Interconnects"
K. Banerjee et al. - "Interconnect Modeling and Analysis in the Nanometer Era: Cu and Beyond"
R. Suaya et al. - "Modeling and Extraction of Nanometer Scale Interconnects: Challenges and Opportunities"
February 1
Lecture Note : Lecture 6
February 6
Lecture Note : Lecture 7
References :
S. Im et al. - "Scaling Analysis of Multilevel Interconnect Temperatures for High Performance ICs"
K. Banerjee et al. - "3-D ICs: A Novel Chip Design for Improving Deep Submicron Interconnect Performance and Systems-on-Chip Integration"
K. Banerjee and N. Srivastava - "Are Carbon Nanotubes the Future of VLSI Interconnections?"
February 8
Lecture Note : Lecture 8
References :
T. Sakurai and A.R. Newton - "Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas"
K. Roy et al. - "Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits"
L.R. Harriott - "Limits of Lithography"
J.D. Plummer and P.B. Griffin - "Material and Process Limits in Silicon VLSI Technology"
R.W. Keyes - "Explaining Strain"
K. Rim et al. - "Fabrication and Analysis of Deep Submicron Strained-Si n-MOSFET's Electron Devices"
T. Mizuno et al. - "Novel SOI p-Channel MOSFETs With Higher Strain In Si Channel Using Double SiGe Heterostructures"
M. Ieong et al. - "Comparison of Raised and Schottky Source/Drain MOSFETs Using a Novel Tunneling Contact Model"
C. Wang et al. - "Sub-40 nm PtSi Schottky Source/Drain Metal-Oxide-Semiconductor Field-Effect Transistors"
J. Kedzierski et al. - "Complementary Silicide Source/Drain Thin-Body MOSFETs for the 20 nm Gate Length Regime"
E. Josse and T. Skotnicki - "Polysilicon Gate With Depletion-or-Metallic Gate With Buried Channel: What Evil Worse?"
E.P. Gusev et al. - "Ultrathin High-K Gate Stacks for Advanced CMOS Devices"
D.A. Antoniadis - "SOI CMOS As A Mainstream Low-Power Technology: A Critical Assessment"
M.M. Pelella and J.G. Fossum - "On the Performance Advantage of PD/SOI CMOS With Floating Bodies"
J.P. Colinge - "Fully-Depleted SOI CMOS for Analog Applications"
R. Chau et al. - "A 50 nm Depleted-Substrate CMOS Transistor (DST)"
February 13
Lecture Note : Lecture 9
References :
R.H. Dennard et al. - "Design of Ion-Implanted MOSFET’s with Very Small Physical Dimensions"
H-S. P. Wong et al. - "Nanoscale CMOS"
D.J. Frank et al., - "Device Scaling Limits of Si MOSFETs and Their Application Dependencies"
J.P. Colinge - "Silicon-On-Insulator Gate-All-Around Device"
H-S. P. Wong et al. - "Device Design Considerations for Double-Gate, Ground-Plane and Single-Gated Ultra-Thin SOI MOSFET's at the 25 nm Channel Length Generation"
J.T. Park, J.P. Colinge - "Multiple-Gate SOI MOSFETs: Device Design Guidelines"
Y.K. Choi et al. - "Sub-20 nm CMOS FinFET Technologies"
F.L. Yang et al. - "25 nm CMOS Omega FETs"
M. Jurczak et al. - "Silicon-on-Nothing (SON) - An Innovative Process for Advanced CMOS"
J.M. Hergenrother et al. - "The Vertical Replacement-Gate (VRG) MOSFET: A 50-nmVertical MOSFET with Lithography-Independent Gate Length"
February 15
Lecture Note : Lecture 10
February 20
Lecture Note : Lecture 11
February 22
Lecture Note : Lecture 12
February 27
Lecture Note : Lecture 13
March 2
Lecture Note : Lecture 14
Last updated on March 26,2007