University of California, Santa Barbara
Department of Electrical and Computer Engineering

Digital Design Principles

ECE 152A - Summer 2011

Instructor: Professor John J. Shynk

Announcements:

6-2-11: The first class meeting is on Monday, June 20 (3:30 - 4:50 p.m.).

Instructor Office Hours:

Monday and Wednesday, 5:00 - 6:00 p.m., HFH 3123.

Course Information:

Design of synchronous digital systems: timing diagrams, propagation delay, latches and flip-flops,
shift registers and counters, Mealy/Moore finite state machines, Verilog, 2-phase clocking, timing analysis,
CMOS implementation, S-RAM, RAM-based designs, ASM charts, state minimization.

Labs:

Grading:

Homework 15% (weekly)
Lab 20% (weekly)
Midterm Exam 30% (Wednesday, July 27, 3:30 - 4:30 p.m.)
Final Exam 35% (Wednesday, August 24, 3:30 - 4:50 p.m.)

Required Textbook:

Brown & Vranesic, Fundamental Digital Logic with Verilog Design, McGraw-Hill, 2nd Edition, 2008

Lecture Handouts:

• #1 Course Information

Lecture Slides by Dr. Johnson (overlap with our lecture days):

• Introduction (6-20-11)

Lab Information:

• ECE Shop - List of Available Parts
• Lab Data Sheets (many files here)
• UCSB ECE DigiLab FPGA Board

Lab Handouts:

• Lab 1 - Seven Segment Indicator

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Last Updated: June 7, 2011