University of California, Santa Barbara
Department of Electrical and Computer Engineering

Digital Design Principles

ECE 152A - Summer 2010

Instructor: Professor John J. Shynk

Announcements:

8-19-10: Reminder: The final exam will be held on Wednesday, August 25.
Note that it will be open book, but closed notes/homework/calculator/etc.
8-11-10: The following changes have been made to Homework 7.
Problem 8.12: (i) Verify the minimum state table using a state
diagram. (ii) Convert the FSM to a Mealy machine. (iii) Use row matching
to minimize the Mealy machine and sketch a state diagram. Fifth Problem:
Verify that the Moore machine in Problem 8.12 is minimal using
an implication table.
8-9-10: An example final exam has been posted below.
7-25-10: A second example midterm exam has been posted below (though
not all those topics will be on your midterm exam.)
7-20-10: Reminder: The midterm exam will be held on Wednesday, July 28.
7-16-10: An example midterm exam has been posted below.
6-28-10: Holiday on Monday, July 5. No class or lab.
6-23-10: The grading distribution has been added below.
6-9-10: The first class meeting is on Monday, June 21 (12:30 - 1:50 p.m.).

Instructor Office Hours:

Monday and Wednesday 2:00 - 3:00 p.m., HFH 3123.

Course Information:

Design of synchronous digital systems: timing diagrams, propagation delay, latches and flip-flops,
shift registers and counters, Mealy/Moore finite state machines, Verilog, 2-phase clocking, timing analysis,
CMOS implementation, S-RAM, RAM-based designs, ASM charts, state minimization.

Labs:

Grading:

Homework 15% (weekly)
Lab 20% (weekly)
Midterm Exam 30% (Wednesday, July 28, 12:30 - 1:30 p.m.)
Final Exam 35% (Wednesday, August 25, 12:30 - 1:50 p.m.)

Required Textbook:

Brown & Vranesic, Fundamental Digital Logic with Verilog Design, McGraw-Hill, 2nd Edition, 2008

Lecture Handouts:

• #1 Course Information
• #2 Homework 1 (due June 25)
• #3 Homework 2 (due July 2)
• #4 Homework 1 Solutions (distributed in class)
• #5 Homework 3 (due July 9)
• #6 Homework 2 Solutions (distributed in class)
• #7 Homework 4 (due July 16)
• #8 Homework 3 Solutions (distributed in class)
• #9 Homework 5 (due July 23)
• #10 Homework 4 Solutions (distributed in class)
• #11 Homework 5 Solutions (distributed in class)
• #12 Midterm Exam
• #13 Homework 6 (due August 6)
• #14 Midterm Exam Solutions (distributed in class)
• #15 Homework 7 (due August 13)
• #16 Homework 6 Solutions (distributed in class)
• #17 Homework 8 (due August 20)
• #18 Homework 7 Solutions (distributed in class)
• #19 Homework 8 Solutions (distributed in class)
• #20 Final Exam
• #21 Final Exam Solutions

Lecture Slides by Dr. Johnson (overlap with our lecture days):

• Introduction (6-21-10)
• Boolean Algebra (6-23-10)
• Karnaugh Maps (6-28-10)
• Circuit Timing (6-30-10)
• Digital Integrated Circuits (addendum)
• Adders and Verilog (7-7-10)
• Latches (7-12-10)
• Flip Flops (7-14/19-10)
• Sequential Circuit Design and Verilog (7-21-10)
• Mealy and Moore Machines (7-21/26-10)
• Sequence Detector (7-26/8-2-10)
• Machine Minimization (8-4-10)
• RAM and ROM (8-4/9-10)
• Controller Design (8-9-10)
• Logic Building Blocks (8-11/16-10)
• Design Methodologies (8-18/23-10)

Lab Information:

• ECE Shop - List of Available Parts
• Lab Data Sheets (many files here)
• UCSB ECE DigiLab FPGA Board

Lab Handouts:

• Lab 1 - Seven Segment Indicator
• Lab 2 - Design of Adders
• Lab 3 - Implement a Counter
• Lab 4 - Finite State Machine
• Test Code
• State Machine Code

Previous Exams:

• Example Midterm Exam 1
• Solutions 1
• Example Midterm Exam 2
• Solutions 2
• Example Final Exam
• Solutions

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Last Updated: August 25, 2010