152 Data Sheets

University of California, Santa Barbara
Department of Electrical and Computer Engineering

Digital Design Principles

LAB DATA SHEETS

Lab #1

Lab #2

Lab #3

HardwareNotes	XESS - 50 Manual referenced from http://www.xess.com
Xilinx Software	Digital I/O Board
Borland C	Borland C Universal Library
ModelSim	Update to Universal Lib Example - unilib.c
testbench.v - Sample Testbench
Verilog Tutorials
Verilog According to Tom	Verilog in One Day referenced from http://www.deeps.org/Verilog/veritut.html

Lab #4