http://www.ece.ucsb.edu/courses/ECE225/225_W23Banerjee/ | https://tinyurl.com/ECE225-W23 Course Info | Lecture Notes & Refs | Resources - ECE 225   High-Speed Digital Integrated Circuit Design   UCSB, ECE, Winter 2023 - Instructor: Prof. Kaustav Banerjee   kaustav (at) ece.ucsb.edu   Office: Harold Frank Hall (HFH) 4151   Phone: (805) 893-3337   Office Hour: Flexible, appointment by email. - Grader: Ankit Kumar   ankitkumar (at) ece.ucsb.edu   Office: HFH 2164   Office Hour: appointment by email. - Classroom: ESB 1003 - Schedule: Tue & Thu 4:00PM-5:50PM - For more info, please click HERE. -Assignment 1 - Due Feb 17th 12:00 PM via GradeScope -Assignment 2 - Due Mar 10h 12:00 PM via GradeScope Final Project Report Format: [1] WORD [2] LATEX   Lecture 1 - Overview Reference(s):  1. G. E. Moore, "Cramming More Components onto Integrated Circuits"   2. P. Gelsinger, "Microprocessors for the New Millennium: hallenges, Opportunities, and New Frontiers"  3. S. Borkar, et. al, "Parameter Variations and Impact on Circuit and Microarchitecture"       Lecture 2 - Discussion of Project Topics       Lecture 3 - Review of CMOS Design       Lecture 4 - Review of Semiconductor Physics     Lecture 5 - MOSFET Scaling   References: 1. S. Thompson, et al, "MOS Scaling: Transistor Challenges for the 21st Century" 2. E. P. Gusev, et al, "Advanced high-k dielectric stacks with polySi and metal gates: Recent progress and current challenges" 3. W. Haensch, et al, "Silicon CMOS devices beyond scaling" 4. X. Huang, et al, "Sub-50 nm P-Channel FinFET" 5. S. H. Rasouli, et al, "Design Optimization of FinFET Domino Logic Considering the Width Quantization Property" 6. J. A. Hutchby, et al, "Extending the Road Beyond CMOS"       Lecture 6 - Interconnects I References: 1. W. C. Elmore, "The Transient Response of Damped Linear Networks" 2. W. Nagen et al., "Interconnect-Power Dissipation in a Microprocessor" 3. Suaya, et al, "Modeling and Extraction of Nanometer Scale Interconnects: Challenges and Opportunities"       Lecture 7 - Interconnects II References: 1. A. Deutsch et al., "When are Transmission-Line Effects Important for On-Chip Interconnections?" 2. K. Banerjee and A. Mehrotra, "Analysis of On-Chip Inductance Effects for Distributed RLC Interconnects" 3. K. Banerjee, et. al., "Interconnect Modeling and Analysis in the Nanometer Era: Cu and Beyond"       Lecture 8 - Non-Classical CMOS Devices References: 1. R. H. Yan, et al, “Scaling the Si MOSFET: From Bulk to SOI to Bulk” 2. S. Rasouli, et al., "Design optimization of FinFET Domino logic considering the width quantization property". IEEE Trans. Elec. Dev., vol. 57, no. 11, 2934-2943 (2010). 3. G. Yeap, et al. "5nm CMOS production technology platform featuring full-fledged EUV and high-mobility channel FinFETs with densest 0.021µm2 SRAM Cells for mobile SoC and high-performance computing applications". In IEEE International Electron Devices Meeting 879–882 (IEEE, 2019). 4. N. Loubet, et al. "Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET". In IEEE VLSI Technology Symposium 230-231, (IEEE, 2017). 5. H. Jagannathan, et al. "Vertical-transport nanosheet technology for CMOS scaling beyond lateral-transport devices". In IEEE International Electron Devices Meeting 557-560 (IEEE, 2021).       Lecture 9 - Steep Subthreshold Slope Devices   References: 1. W. Cao, et al. "Subthreshold-swing physics of tunnel field-effect transistors". In AIP Advances, Vol. 4, pp. 067141, 2014. 2. D. Sarkar, et al. "A subthermionic tunnel field-effect transistor with an atomically thin channel". In Nature, Vol. 526, pp. 91-95, 2015. 3. W. Cao, et al. "Designing Band-to-Band Tunneling Field-Effect Transistors with 2D Semiconductors for Next Generation Low-Power VLSI". In IEEE International Electron Devices Meeting (IEEE, 2015). 4. W. Cao, et al. "Is Negative Capacitance FET a Steep-slope Logic Switch?". In Nature Communications, 11, 196, pp. 1-8, January 10, 2020.       Lecture 10 - Interconnect Design   References: 1. A. H. Ajami, K. Banerjee et al., "Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI". In Analog Integrated Circuits and Signal Processing volume 42, pages 277–290 (2005). 2. A. H. Ajami, K. Banerjee et al., "Modeling and Analysis of Non-Uniform Substrate Temperature Effects on Global ULSI Interconnects". In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, 6, 2005. 3. K. Banerjee et al., "A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs". In IEEE TED, vol. 49, 11, 2002.       Lecture 11 - Interconnect Design II   References: 1. V. Wason and K. Banerjee, "A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations" In Proceedings of the 2005 International Symposium on Low Power Electronics and Design, pp. 131-136, 2005. 2. K. Banerjee et al., "Global (Interconnect) Warming". In IEEE Circuits and Devices Magazine, vol. 17, no. 5, pp. 16-32, 2001.     Lecture 12 - Power Dissipation in Nanoscale ICs   References: 1. S. Borkar "Low power design challenges for the decade". In Proceedings of the ASP-DAC 2001, pp. 293-296, 2001. 2. T. Kuroda "CMOS design challenges to power wall". In International Microprocesses and Nanotechnology Conference, pp. 6-7, 2001. 3. T. Sakurai "Perspectives of Low-Power VLSI's". In IEICE Trans. Electron, vol. E87-C, 2004. 4. H. Dadgour, et al. "A Statistical Framework for Estimation of Full-Chip Leakage-Power Distribution Under Parameter Variations". In Trans. Elec. Dev., vol. 54, no. 11, 2930-2945 (2007).       Lecture 13 - Nanoscale Power and Thermal Management   References: 1. S. C. Lin, K. Banerjee et al. "A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs Part I: Electrothermal Couplings and Full-Chip Package Thermal Model". In IEEE TED, vol. 54, 12, pp. 3342-3350, 2007. 2. S. C. Lin, K. Banerjee et al. "A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part II: Implementation and Implications for Power Estimation and Thermal Management". In IEEE TED, vol. 54, 12, pp. 3351-3360, 2007. 3. S. C. Lin, K. Banerjee et al. "A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies". In IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, 11, 2008. 4. S. C. Lin, K. Banerjee et al. "Cool Chips: Opportunities and Implications for Power and Thermal Management". In IEEE Transactions on Electron Devices, vol. 55, 1, 2008.       Lecture 14 - Metal-Gate Work-Function Variability in Emerging Device Technologies   References: 1. H. F. Dadgour, K. Banerjee et al. "Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part I: Modeling, Analysis, and Experimental Validation". In IEEE TED, vol. 57, 10, pp. 2504-2514, 2010. 2. H. F. Dadgour, K. Banerjee et al. "Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part II: Implications for Process, Device, and Circuit Design". In IEEE TED, vol. 57, 10, pp. 2515-2525, 2010.       Lecture 15 - A Novel Variation-Aware Low-Power Keeper Architecture for Wide Fan-in Dynamic Gates   References: 1. H. F. Dadgour, K. Banerjee et al. "A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates". In IEEE TED, vol. 18, 11, pp. 1567-1577, 2010.       Lecture 16 - 3-D Integrated Circuits   References: 1. K. Banerjee et al. "3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration". In Proceedings of IEEE, vol. 89, 5, pp. 602-633, 2001. 2. C. Xu et al. "Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs". In IEEE TED, vol. 57, 12, pp. 3405-3417, 2010. 3. J. Jiang et al. "Ultimate Monolithic-3D Integration With 2D Materials: Rationale, Prospects, and Challenges". In IEEE Journal of the Electron Deivces Society, vol. 7, pp. 878-887, 2019. 4. D. Zhang et al. "0.5T0.5R—An Ultracompact RRAM Cell Uniquely Enabled by van der Waals Heterostructures". In IEEE TED, vol. 68, 4, pp. 2033-2040, 2021.       Lecture 17 - Memory   References: 1. R. W. Mann et al. "Ultralow-power SRAM technology". In IBM Journal of Research and Development, vol. 47, pp. 553-566, 2003. 2. J. A. Mandelman et al. "Challenges and future directions for the scaling of dynamic random-access memory (DRAM)" In IBM Journal of Research and Development, vol. 46, pp. 187-212, 2002. 3. J. Akerman "Toward a Universal Memory". In Science, vol. 308, pp. 508-510, 2005. 4. W. Cao et al. "Can 2D-Nanocrystals Extend the Lifetime of Floating-Gate Transistor Based Nonvolatile Memory?" In IEEE TED, vol. 61, pp. 3456-3464, 2014. 5. S. Raoux et al. "Phase change materials and phase change memory" In MRS Bulletin, vol. 39, pp. 703-710, 2014. 6. D. Zhang et al. "0.5T0.5R—An Ultracompact RRAM Cell Uniquely Enabled by van der Waals Heterostructures". In IEEE TED, vol. 68, 4, pp. 2033-2040, 2021.                                                                                                                                 - Simulation software: (Manuals) - Circuit Netlist Simulator: HSpice - Analog Modeling: Verilog-A - Waveform viewer: CScope - Waveform viewer: AvanWaves - Circuit Layout Editor: MAX - Schematic Capture Program: SUE - Please do NOT print copies of these manuals! - For other tools, see Computer/Network Support - To set up the environment for your work,   see Environment Setup Guidance .   -Latest snippet to be added to .bashrc file  - ECE 122A - VLSI Principles, Fall 2022 - Nanoelectronics Research Lab

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