Department of Electrical and Computer Engineering
Digital Design
Principles
ECE
Prof. Volkan Rodoplu
Lectures: Monday/Wednesday
3:30 - 4:45 pm at TD 2600.
(Note the Location !!!: Theater Dance 2600. This is next to the
Humanities Building.)
Professor's Office hours: 5:00 - 6:00
PM, Mondays and Wednesdays,
in Room 4113, Harold Frank Hall; starting October 15,
2007.
Midterm Exam: in class,
see course calendar in Syllabus
Final Exam:
Announcements
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12/08/07: Finals Week TA office hours will be:
11/28/07: Students who are planning to
use the "late check-out" option below, on parts of Lab # 5, should
also utilize the TA office hours during the week, for their late check-out,
if they are done; that is, you may do your late check-out, during the TA
office hours (e.g. Wednesday, December 5, 2007, 5:00 - 6:30 PM), if you are
done, rather than waiting for the final date. This will alleviate the load on
12:00 PM - 2:00 PM, December 7, 2007. 11/27/07: LAB # 5 Grading: Lab # 5 will
be graded as follows: For any part of the lab that has been completed on time
(by the Lab # 5 deadline in your lab section), we will multiply your score
for that part by 1.0. Now, we will also allow teams to complete any parts
that they could not complete, by 11/09/07: MIDTERM MATERIAL AND STUDY
GUIDELINES: The midterm exam will take place on
Wednesday, November 14, 2007, 3:30 - 4:45 PM in class, during the regular
class time. Please arrive at least 5 minutes before the exam starts. We will
start at The midterm will cover up to the end of
Lecture 5-6 on the web page, until the end of the shift register design
section, which appears toward the end of those lecture notes. It also covers
until the end of HW # 2, and the end of Lab # 3. In particular, formal methodologies for
the design of finite state machines (Mealy/Moore machines, Lecture 7 in the
lecture notes below), and Lab # 4 will not be on the midterm. A recommended way to study for the
midterm is to solve the previous years' midterms, which are posted on this
web page, and check your answers against the midterm solutions under the
Homework-Solutions link (where we also post homework solutions.) 11/05/07: Class has been cancelled
today, Monday November 5th, 2007. 10/31/07: HW # 3 through 5 deadline:
Homework # 3 is due November 21, 2007, WEDNESDAY. This deadline remains the
same. Since it is due Thanksgiving week, and we cannot have a Friday
deadline. The deadlines for Homework # 4 and Homework # 5 have been updated
to Fridays. The deadlines below in the homework section are all up-to-date. 10/22/07: For HW #1, Problem # 8 of the
Course Reader: If you have found the minimum SOP expression for each of the
outputs of this circuit, and yet your implementation uses more than 11 gates,
this is fine. We will give you full credit. 10/22/07: For Lab # 2, pre-lab:
"Sketch the schematic": We are looking for a rough sketch here,
rather than an exact drawing. For example, how many logic levels will there
be? How many rows will there be (e.g. in the AND-OR array)? How is the fan-in
growing for the inputs to the first level of this logic? We would like your
sketch to show those. It would help to write down at least some of the
equations, but if things are getting very long, we would like you to
visualize, for example, how many product terms there will be when everything
is multiplied out? What kind of circuit this corresponds to? What's the
maximum fan-in? Show these. These are the questions we are interested in,
rather than the exact wiring, in this sketch. 10/17/07: LAB # 1: Because of the problems with the primary
domain controller, you will be allowed to DEMO your Lab # 1, Part # 4 (TTL
implementation) in the TA office hours in the week of October 22, in addition
to your laboratory section. We encourage you to demo your Lab # 1 by the end
of the 1st hour of the lab section, so that you don't fall behind in your Lab
# 2. However, you will be allowed to demo during ANY of the TA office hours
in the week of October 22, if you are not able to demo correctly in your own
lab section. The TA office hours appear in the "TA lab sections and
office hours" section below. (Please also note that Lab # 1, Part # 3
(the Simulation) will not be graded. Please move onto your TTL
implementation.) * We are keeping the current (original)
lab sections (1 on Monday, and 2 on Tuesday). The numbers of students we have
for the lab sections are reasonable right now (less than or equal to 25). Do
not worry about the section's being "full" on GOLD. * For this week only, we will offer an
additional lab section 7:30 - 10:20 PM on Thursday, October 11, 2007. But
this is only for this week, for people who missed their lab session. This
will NOT be offered as a regular section, and will cease to exist next week. |
(Homework is assigned from the reader.)
CourseReader_Problems 10 to 14
Homework - Solutions
The homework is due
in the ECE
(After you exit the
elevator, go straight through the double doors across from you. The homework
box is outside after you go through the double doors.)
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(due
October 24, 2007; 2:00 PM) For HW
# 1, PLEASE SKIP PROBLEM # 6. DO THE
REST OF THE PROBLEMS. |
(due
October 31, 2007; 2:00 PM) For HW
# 2: PLEASE SKIP PROBLEMS 3, AND 9. (These are B & V Problem 7.32, and Problem # DO THE
REST OF THE PROBLEMS. |
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(due
November 26, 2007; Monday, 2:00 PM) For HW
# 3: PLEASE SKIP PROBLEMS 1-3 (the B&V textbook problems). Do the REST of
the Problems, which are from the Course Reader. (Start
early!) (Note:
This homework is due Wednesday, November 21; note that this is Thanksgiving
week, so we cannot have a Friday deadline.) |
(due
November 30, 2007; Friday, 2:00 PM) |
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(due
December 7, 2007; Friday, 2:00 PM) |
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Grading Guidelines for Homeworks
and Labs
Lab Handouts
Lab Schedule
Print out Data Sheets
for each lab
ECE Shop: List of
Available Parts
UCSB/ECE DigiLab FPGA Board
Information
ALL PRE-LABS DUE ARE AT THE BEGINNING OF YOUR LAB.
THE CHECK-OUTS FOR DEMOS MUST BE DONE WITHIN FIRST
1 HR. OF THE LAB SECTION.
All the lab dates below are for "week of"
the date indicated,
at the beginning of your lab section.
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Nothing is due: October 8, 2007 (but
highly encouraged to complete as much of Steps # 1 and # 2 as possible.) Pre-lab due: (Steps # 1 and # 2 due)
October 15, 2007. [Demo of Steps # 3 and/or # 4 encouraged, but
not required.] Check-out (Steps # 3 and # 4): October
22, 2007 |
Pre-lab due: October 22,
2007 [This is a long pre-lab; start early!] Check-out: October 29, 2007 |
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Lab starts: October 29, 2007 Check-out: November 5, 2007 (Hint: Use teamwork to manage the
wiring to get it done by the deadline.) |
Lab
# 4 Lab-4 help Sample C program cbw.h cbw32bc.lib lab4_verilog Sample-Testbench
cbw32.dll Lab starts: November 5, 2007 (There is no pre-lab for this lab.) Part 1 due: November 12, 2007 Parts 2, 3 and 4 due: November 19, 2007 |
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Lab starts: November 19, 2007 (There is no pre-lab for this lab.) Parts 1 and 2 due: November 26, 2007 Parts 3 and 4 due: December 3, 2007 |
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Lab Sections and TA Office Hours
Harold Frank Hall, Room 1124 (DigiLab)
You may go to
the office hours of any TA (not just the TA of your lab section)
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Kunal Arya Lab Section: Tue:
2:00 – 4:50 pm Office
hours: Tue:
12:30 – 2:00 pm |
Sheng-Luen Wei ("Vincent") Lab
Section: Mon:
10:00 – 12:50 am Office
hours: Mon: 1:30
– 3:00 pm |
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Vivek Nandakumar Lab
Section: Tue: 7:00 –
9:50 pm Office
Hours: Wed: 5:00 –
6:30 pm |
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Acknowledgments: We would
like to thank all the professors, TA's and lecturers, who have created, worked on,
used, and revised the laboratories for this course. A partial list is as
follows: Prof. Roger C. Wood, Christian Schmidt, Prof. Kaustav
Banerjee, James Rosenthal, Brian Simolon,
Dr. John M. Johnson, Prof. Volkan Rodoplu,
Aida Todri, Nilesh Modi, Vishal Mehta, James Tandon. We would also like to thank Dr. John M. Johnson for
preparing lecture note slides for this course, and for his continuing
contributions during the summer quarters.
Practice Exams
ECE 152A Midterm Exam Fall 2004
ECE152A_Midterm Exam Winter 2005
ECE 152A Midterm Exam Fall 2005
ECE 152A Midterm Exam Fall
2007
ECE 152A Final Exam Winter 2005
Practice Problems for
FSM Design: PS1 PS2
PS4
Lecture Notes (very
rough)
(The
following are handwritten lecture notes that I made while preparing for the lectures.
These are very rough compared to the exposition in class, and were mostly notes
to myself. However, I am providing them here in case you find them useful.)
. Blocking vs.
Non-blocking Assignments
. (Enrichment (not required): Lecture 10)
Lecture Slides
(prepared by Prof. Johnson)