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http://www.ece.ucsb.edu/courses/ECE225/225_W22Banerjee/ | http://tinyurl.com/ECE225-W22 Course Info | Lecture Notes & Refs | Resources - ECE 225   High-Speed Digital Integrated Circuit Design   UCSB, ECE, Winter 2022 - Instructor: Prof. Kaustav Banerjee   kaustav (at) ece.ucsb.edu   Office: Harold Frank Hall (HFH) 4151   Phone: (805) 893-3337   Office Hour: Flexible, appointment by email. - Classroom: Online via Zoom till Jan 13th.                       ESB 1003, from Jan 18th onwards. - Schedule: Tuesday & Thursday 4:00PM-5:50PM - For more info, please click HERE. - Assignment 1 - Due on Feb 22nd at 10 pm via email to arnab@ucsb.edu - Assignment 2 - Due on March 8th at 10 pm to arnab@ucsb.edu Final Project Report Format: [1] WORD [2] LATEX - Lecture 1 - Overview Reference(s):  1. G. E. Moore, "Cramming More Components onto Integrated Circuits"  2. P. Gelsinger, "Microprocessors for the New Millennium: hallenges, Opportunities, and New Frontiers" 3. S. Borkar, et. al, "Parameter Variations and Impact on Circuit and Microarchitecture" - Lecture 2 - Discussion of Project Topics - Lecture 3 - Semiconductor Device Physics - Lecture 4 - CMOS Digital Design (Review) - Lecture 5 - Interconnects - Part I References: 1. W. C. Elmore, "The Transient Response of Damped Linear Networks" 2. W. Nagen et al., "Interconnect-Power Dissipation in a Microprocessor" - Lecture 6 - Interconnects - Part II References: 1. R.Suaya, K.Banerjee,  et al., "Modeling and Extraction of Nanometer Scale Interconnects: Challenges and Opportunities" 2. K. Banerjee, et. al., "A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs" 3. A. Deutsch et al., "When are Transmission-Line Effects Important for On-Chip Interconnections?" 4. K. Banerjee and A. Mehrotra, "Analysis of On-Chip Inductance Effects for Distributed RLC Interconnects" 5. K. Banerjee, et. al., "Interconnect Modeling and Analysis in the Nanometer Era: Cu and Beyond"  - Lectures 7 - Interconnect Design under Thermal, Power, Reliability, & Variability Constraints References: 1. A. H. Ajami, K. Banerjee et al., "Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI" 2. A. H. Ajami, K. Banerjee et al., "Modeling and Analysis of Non-Uniform Substrate Temperature Effects on Global ULSI Interconnects" 3. K. Banerjee et al., "A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs" - Lectures 8 - Interconnect Design under Thermal, Power, Reliability, & Variability Constraints (Cont'd) References: 1. V. Wason and K. Banerjee, "A Probabilistic Framework for Power-Optimal Repeater Insertion for Global Interconnects Under Parameter Variations" 2. K. Banerjee et al., "Global (Interconnect) Warming" - Lectures 9 - MOSFET Scaling References: 1. R. Dennard, et al, “Design of Ion Implanted MOSFETs with Very Small Physical Dimensions” 2. Kelin J. Kuhn, et al, “Considerations for Ultimate CMOS Scaling” - Lectures 10 - MOSFET Scaling (Cont'd) References: [1] R. H. Yan, et al, “Scaling the Si MOSFET: From Bulk to SOI to Bulk” [2] S. Rasouli, et al., Design optimization of FinFET Domino logic considering the width quantization property. IEEE Trans. Elec. Dev., vol. 57, no. 11, 2934-2943 (2010). [3] G. Yeap, et al. 5nm CMOS production technology platform featuring full-fledged EUV and high-mobility channel FinFETs with densest 0.021µm2 SRAM Cells for mobile SoC and high-performance computing applications. In IEEE International Electron Devices Meeting 879–882 (IEEE, 2019). [4] N. Loubet, et al. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. In IEEE VLSI Technology Symposium 230-231, (IEEE, 2017). [5] H. Jagannathan, et al. Vertical-transport nanosheet technology for CMOS scaling beyond lateral-transport devices. In IEEE International Electron Devices Meeting 557-560 (IEEE, 2021). - Lectures 11 - Steep Subthreshold Slope (SS) Devices: Tunneling Field-Effect-Transistors References: 1. W. Cao et al., "Subthreshold-Swing Physics of Tunnel Field-Effect Transistors" 2. Y. Khatami and K. Banerjee, "Steep Subthreshold Slope n- and p-type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits" 3. R. Gandhi, K. Banerjee et al., "CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs with <= 50-mV/decade Subthreshold Swing" 4. K. Tomioka, M. Yoshimura, T. Fukui. Steep-slope tunnel field-effect transistors using III–V nanowire/Si heterojunction. IEEE Symposium on VLSI Technology, 47–48, (IEEE, 2012). 5. D. Sarkar, K. Banerjee et al., "A Subthermionic Tunnel Field-Effect Transistor with an Atomically Thin Channel" - Lectures 12 - Power Dissipation in Nanoscale ICs References: 1. S. Borkar, "Low Power Design Challenges for the Decade" 2. T. Kuroda, "CMOS Design Challenges to Power Wall" 3. T. Sakurai, "Perspectives of Low-Power VLSI's" - Lectures 13 - Nanoscale Power and Thermal Management References: 1. S. C. Lin, K. Banerjee et al., "A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs Part I: Electrothermal Couplings and Full-Chip Package Thermal Model"  2. S. C. Lin, K. Banerjee et al., "A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs Part II: Implementation and Implications for Power Estimation and Thermal Management"  3. S. C. Lin and K. Banerjee, "A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies"  4. S. C. Lin and K. Banerjee, "Cool Chips: Opportunities and Implications for Power and Thermal Management" - Lectures 14 - Metal-Gate Work-Function Variability in Emerging Device Technologies References: 1. H. F. Dadgour, K. Banerjee et al., "Grain-Orientation Induced Work-Function Variation in Nanoscale Metal-Gate Transistors -- Part I: Modeling, Analysis, and Experimental Validation" 2. H. F. Dadgour, K. Banerjee et al., "Grain-Orientation Induced Work-Function Variation in Nanoscale Metal-Gate Transistors -- Part II: Implications for Process, Device, and Circuit Design"  Lectures 15 - 3D Integrated Circuits References: 1. K. Banerjee, et al, "3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration"  2. C. Xu, et al, "Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs" 3. J. Jiang, et al, "Ultimate Monolithic-3D Integration with 2D Materials: Rationale, Prospects, and Challenges" 4. D. Zhang et al., 0.5T0.5R—An Ultracompact RRAM Cell Uniquely Enabled by van der Waals Heterostructures  Lectures 16 - Semiconductor Memories References: 1. R. W. Mann, et al., "Ultralow-power SRAM technology" 2. J. A. Mandelman, et al., "Challenges and future directions for the scaling of DRAM" 3. J. Akerman, "Toward a Universal Memory" 4. X. Xie, et al., "Room Temperature 2D Memristive Transistor with Optical Short-Term Plasticity" 5. S. Raoux, et al., "Phase Change Materials and Phase Change Memory" 6. D. Zhang, C.H. Yeh, et al, "0.5T0.5R—An Ultracompact RRAM Cell Uniquely Enabled by van der Waals Heterostructures" 7. D. Strukov, "The missing memristor found" Lectures 17 - Timing and Clocking Reference: 1. K. Bowman, et al., "Impact of die-to-die and within-die parameter fluctuations on the mazimum clock frequency distribution for gigascale integration" Lectures 18 - A Novel Variation-Aware Low-Power Keeper Architecture for Wide Fan-in Dynamic Gates Reference: [1] H. F. Dadgour and K. Banerjee "A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic Or Gates"   - Simulation software: (Manuals) - Circuit Netlist Simulator: HSpice - Analog Modeling: Verilog-A - Waveform viewer: CScope - Waveform viewer: AvanWaves - Circuit Layout Editor: MAX - Schematic Capture Program: SUE - Please do NOT print copies of these manuals! - For other tools, see Computer/Network Support - To set up the environment for your work,   see Environment Setup Guidance . - ECE 122 - VLSI Principles, Fall 2021 - Nanoelectronics Research Lab

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Nanoelectronics Research Lab