ECE 152A - Winter 2004

Announcements

3/8/04: Final Review Solutions posted.

3/6/04: Calculators will allowed on the Final. They may not be used to store equations or information about the course.

3/6/04: The Final will be closed book, closed notes.

3/6/04: Try the Final review questions before class on Monday & Wednesday (Homework Section)

3/6/04: Exam 3 Solutions posted

3/3/04: See the percentage that each lab is worth - in the Lab Handouts Section

3/3/04: See updated solution for 7_28 in Homework Section

3/2/04: Solution of Latch Setup time explained in Discussions Section

3/1/04: See update on how to submit your portfolio for EXTRA CREDIT

3/1/04: Final Project grade breakdown posted

Homework - Solutions
All "due" dates are only recommend due dates. No homework will be turned in.
Students are strongly encouraged to work out all problems.

Homework #1 - Due Jan14 Do the following problems from the textbook^*: 2.5, 2.6, 2.18, 4.1, 4.2, 4.16, 4,17	Homework #2 Do the following problems from the textbook^*: 4.7, 4,8, 4.9, 4.19, 4.25, 4.26, 5.5, 5.13, 5.24, 6.2, 6.15
Chapter 8 Design Problems - Test Prep	Homework #3 Do the following problems from the textbook^*: 11.6, 11.9, 11.10, 11.19, 11.21, 13.4, 13.7, 13.8, 13.11, 13.19, 13.20, 14.7, 14.12, 14.20, 14,29, 14.32, 14.34
Verilog Homework	Homework #4 Do the following problems from the textbook^*: 11,16, 11.17 13.17, 13.18 14.4, 14,8
Homework #4 Do the following problems from the textbook^*: 9.2, 9.4, 9.7, 9.16, 9.20, 9.21, 9.23, 9.26, 9.28, 9.30, 9.32	RAM Homework p382 of Katz (ram.pdf), Problems 7.26 - 7.30
Homework #5 Do the following problems from the textbook^*: 15.12, 15.14, 15.20, 15.28, 15,29, 15.30	FINAL Exam Review Problems Review1: Problem 2, 3 Review2: Problem 3, 6 Review3: Problem 1, 3, 4, 5 Review4: Problem 1, 2, 3, 5, 6
^{* Fundamentals of Logic Design, Charles H. Roth, Jr., 5th Edition}

Lab Handouts
Lab Schedule
Print out Data Sheets for each lab

Lab #1 - Grading	Lab #2 - Grading
Lab #3 - Grading	Lab #4 - Grading
Final Project - Grading	Lab Grade Breakdown

Lab Sections
Engr I, Room 1124

Tuesday 2:00 - 4:50 pm TA: Brian Simolon	Tuesday 7:00 - 9:50 pm TA: James Rosenthal
Wednesday 7:00 - 9:50 pm TA: Arash Arfaee	Thursday 7:00 - 9:50 pm TA: Christian Schmidt

TA Office Hours

Brian Simolon sim@umail.ucsb.edu Engr I, Room 1124 Thursday 2:00 - 3:00	James Rosenthal jrosen00@umail.ucsb.edu Engr I, Room 1124 Thursday 1:00 - 2:00
Arash Arfaee Arash@ece.ucsb.edu Engr I, Room 1124 Wednesday 2:00-3:00	Christian Schmidt schmidt@ece.ucsb.edu Engr I, Room 1124 Wednesday 9:30-10:30
Mark Leonhardt (Tutor) kma@umail.ucsb.edu Engr I, Room 1124 Tuesday 5:00 - 7:00

January 5 - 12: Chapters 1-4
January 12 - 19: Chapters 5-8
January 22 - 28: Chapters 11, 13, and 14
January 22 - Feb 9: Verilog Tutorials
verilog vending machine
February 13 - 18: Chapter 9
February 22 - March 1: Chapter 15 - 16
RAM - Randy Katz, Contemporary Logic Design, First Edition, 1993, Section 7.6