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Refrences:
G.E. Moore, "Cramming more Components onto Integrated
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P.P. Gelsinger, "Microprocessors for the
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W. Weber et al., "Ambient Intelligence -
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S. Borkar et al., " Parameter Variations
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ITRS 2005 Overall Roadmap Technology Characteristics Link: http://public.itrs.net/.
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Refrences:
S.H. Gunther et al.,
“Managing the Impact of Increasing Microprocessor Power Consumption,” Intel
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R. Viswanath et al., “Thermal Performance Challenges from
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K. Banerjee, S-C. Lin, A. Keshavarzi, S. Narendra and V.
De, “A Self-Consistent Junction Temperature Estimation Methodology for Nanometer
Scale ICs with Implications for Performance and Thermal
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Refrences:
T. Sakurai and A. R. Newton, “Alpha-power law MOSFET model
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Refrences:
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Refrences:
J. Yuan and C. Svensson, "High-speed CMOS circuit
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Refrences:
Ivan Edward Sutherland et al., Logical Effort : Designing Fast CMOS Circuits, Morgan Kaufmann, 1999.
D. Radhakrishnan et al., "Formal design procedures for
pass transistor switching circuits," IEEE Journal of Solid-State Circuits, vol.
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Lecture Note.
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Refrences:
E. G. Friedman, "Clock distribution networks in
synchronous digital circuits," Proceedings of the IEEE, vol. 89, pp. 665-692,
2001.
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Refrences:
S. Borkar et al., " Parameter Variations and Impact on
Circuits and Microarchitecture," Design Automation Conference, 2003, pp.
338-342.
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D. Boning and S. Nassif, Models of Process Variations in
Device and Interconnect, in /Design of High-Perfromance Microprocessor
Circuits/, editors: Chandrakasan, Bowhill and Fox, IEEE Press.
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K. A. Bowman et al., "Impact of die-to-die and within-die
parameter fluctuations on the maximum clock frequency distribution for gigascale
integration," IEEE Journal of Solid-State Circuits, vol. 37, pp. 183-190, 2002.
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