LECTURE NOTES AND REFERENCES

 

Lecture 1

Lecture Note.

Refrences:

  1. G.E. Moore, "Cramming more Components onto Integrated Circuits," in Electronics, vol. 38, pp. 114 - 117, April 1965.

  2. P.P. Gelsinger, "Microprocessors for the New Millennium: Challenges, Opportunities, and New Frontiers," IEEE International
    Solid-State Circuits Conference, 2001, pp. 22 -25.

  3. W. Weber et al., "Ambient Intelligence - Key Technologies in the Information Age," IEEE International Electron Devices
    Meeting, 2003, pp.3 - 10.

  4. S. Borkar et al., " Parameter Variations and Impact on Circuits and Microarchitecture," Design Automation Conference,
    2003, pp. 338-342.

  5. ITRS 2005 Overall Roadmap Technology Characteristics Link: http://public.itrs.net/.

 

Lecture 1

Lecture Note.

Refrences:

  1. S.H. Gunther et al., “Managing the Impact of Increasing Microprocessor Power Consumption,” Intel Technology Journal 1st quarter, 2001.

  2. R. Viswanath et al., “Thermal Performance Challenges from Silicon to Systems,” Intel Technology Journal 3rd quarter, 2000.

  3. K. Banerjee, S-C. Lin, A. Keshavarzi, S. Narendra and V. De, “A Self-Consistent Junction Temperature Estimation Methodology for Nanometer Scale ICs with Implications for Performance and Thermal
    Management,” IEDM, 2003, pp. 887-890.

 

Lecture 1

Lecture Note.

Refrences:

  1. T. Sakurai and A. R. Newton, “Alpha-power law MOSFET model and its application to CMOS inverter delay and other formulas,” IEEE J. Solid-State Circuits, vol. 25, pp. 584–593, 1990.

 

Lecture 1

Lecture Note.

Refrences:

  1. S. Borkar, "Design challenges of technology scaling," IEEE Micro, vol. 19, 1999 .

 

Lecture 1

Lecture Note.

 

Lecture 1

Lecture Note.

Refrences:

  1. J. Yuan and C. Svensson, "High-speed CMOS circuit technique," IEEE Journal of Solid-State Circuits, vol. 24, pp. 62-70, 1989.

 

Lecture 1

Lecture Note.

Refrences:

  1. Ivan Edward Sutherland et al., Logical Effort : Designing Fast CMOS Circuits, Morgan Kaufmann, 1999.

  2. D. Radhakrishnan et al., "Formal design procedures for pass transistor switching circuits," IEEE Journal of Solid-State Circuits, vol. 20, pp. 531-536, 1985.

 

Lecture 1

Lecture Note.

 

Lecture 1

Lecture Note.

 

Lecture 1

Lecture Note.

 

Lecture 1

Lecture Note.

 

Lecture 1

Lecture Note.

Refrences:

  1. E. G. Friedman, "Clock distribution networks in synchronous digital circuits," Proceedings of the IEEE, vol. 89, pp. 665-692, 2001.

Lecture 1

Lecture Note.

Refrences:

  1. S. Borkar et al., " Parameter Variations and Impact on Circuits and Microarchitecture," Design Automation Conference, 2003, pp. 338-342.

  2. D. Boning and S. Nassif, Models of Process Variations in Device and Interconnect, in /Design of High-Perfromance Microprocessor Circuits/, editors: Chandrakasan, Bowhill and Fox, IEEE Press.

  3. K. A. Bowman et al., "Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration," IEEE Journal of Solid-State Circuits, vol. 37, pp. 183-190, 2002.

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