http://www.ece.ucsb.edu/courses/ECE225/225_S17Banerjee/ | http://tinyurl.com/ECE225S17 Course Info | Lecture Notes & Refs | Assignments | Projects | Resources - ECE225   High-Speed Digital Integrated Circuit Design   UCSB, ECE, Spring 2017 - Instructor: Prof. Kaustav Banerjee   kaustav (at) ece.ucsb.edu   Office: Harold Frank Hall (HFH) 4151   Phone: (805) 893-3337   Office Hour: Fri 1:00-2:00 PM or appointment by email - Classroom: ENGR 2, Room 3301 - Schedule: Tue & Thu 4:00PM-5:50PM - For more info, please click HERE.   Lecture 1 - Overview Reference(s): 1. G. E. Moore, "Cramming More Components onto Integrated Circuits" 2. K. Banerjee, et al, "3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration" 3. S. Im, et al, "Scaling Analysis of Multilevel Interconnect Temperature for High-Performance ICs" 4. D. Sarkar, et al, "A Subthermionic Tunnel Field-Effect Transistor with an Atomically Thin Channel" 5. J. Jiang, et al, "Intercalation Doped Multilayer-Graphene-Nanoribbons for Next Generation Interconnects" Lecture 2 - Discussion of Project Topics Lecture 3 - Semiconductor Physics Review Reference(s): 1. K. Banerjee, et al, "Two-Dimensional Van der Waals Materials" Lecture 4 - MOS & MOSFET Review Lecture 5 - MOSFET Scaling & Non-Classical CMOS   References:   1. T. Skotnicki, et al, "The End of CMOS Scaling"   2. W. Haensch, et al, "Silicon CMOS devices beyond scaling"   3. X. Huang, et al, "Sub-50 nm P-Channel FinFET"   4. S. H. Rasouli, et al, "Design Optimization of FinFET Domino Logic Considering the Width Quantization Property"   5. J. A. Hutchby, et al, "Extending the Road Beyond CMOS" - Lecture 6 - Steep Subthreshold Slope Devices: Tunneling FETs   References:   1. W. Cao et al., "Subthreshold-Swing Physics of Tunnel Field-Effect Transistors"   2. Y. Khatami and K. Banerjee, "Steep Subthreshold Slope n- and p-type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits"   3. R. Gandhi, K. Banerjee et al., "CMOS-Compatible Vertical-Silicon-Nanowire Gate-All-Around p-Type Tunneling FETs with <= 50-mV/decade Subthreshold Swing"   4. D. Sarkar, K. Banerjee et al., "A Subthermionic Tunnel Field-Effect Transistor with an Atomically Thin Channel" - Lecture 7 - CMOS Design (Review)   References:   1. H. F. Dadgour et al., "A Statistical Framework for Estimation of Full-Chip Leakage-Power Distribution Under Parameter Variations" - Lecture 8 - Power Dissipation in Nanoscale ICs   References:   1. K. Banerjee et al., "A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs" - Lecture 9 - VLSI Interconnects   References:   1. K. Banerjee et al., "3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration"   2. R. Suaya, K. Banerjee et al., "Modeling and Extraction of Nanometer Scale Interconnects: Challenges and Opportunities"   3. A. Deutsch et al., "When are Transmission-Line Effects Important for On-Chip Interconnections?" - Lecture 10 - On-Chip Inductance Effects   References:   1. K. Banerjee et al., "Analysis of On-Chip Inductance Effects for Distributed RLC Interconnects"   2. K. Banerjee et al., "Interconnect Modeling and Analysis in the Nanometer Era: Cu and Beyond"   3. R. Suaya, K. Banerjee et al., "Modeling and Extraction of Nanometer Scale Interconnects: Challenges and Opportunities"   4. B. Krauter and S. Mehrotra, "Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis"   5. A. M. Niknejad and R. G. Meyer, "Analysis of Eddy-Current Losses over Conductive Substrates with Applications to Monolithic Inductors and Transformers" - Lecture 11,12 - Interconnect Design under Thermal, Power, Reliability & Variability   References:   1. A. H. Ajami, K. Banerjee et al., "Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI"   2. A. H. Ajami, K. Banerjee et al., "Modeling and Analysis of Non-Uniform Substrate Temperature Effects on Global ULSI Interconnects"   3. A. H. Ajami, K. Banerjee et al., "Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion"   4. K. Banerjee et al., "Global (Interconnect) Warming"   5. K. Banerjee et al., "A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs"   6. V. Wason and K. Banerjee, "A Probabilistic Framework for Power-Optimal Repeater Insertion for Global Interconnects Under Parameter Variations" - Lecture 13 - Nanoscale Power and Thermal Management: Self-consistent Thermal Profile Estimation Design-Specific Metric Optimization IC Cooling Analysis   References:   1. S. C. Lin, K. Banerjee et al., "A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs Part I: Electrothermal Couplings and Full-Chip Package Thermal Model"   2. S. C. Lin, K. Banerjee et al., "A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs Part II: Implementation and Implications for Power Estimation and Thermal Management"   3. S. C. Lin and K. Banerjee, "A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies"   4. S. C. Lin and K. Banerjee, "Cool Chips: Opportunities and Implications for Power and Thermal Mangement" - Lecture 14 - 3-D Integrated Circuits   References:   1. K. Banerjee et al., "3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration"   2. S. Nataranjan et al., "A 14 nm Logic Technology Featured 2nd-generation FinFet, Air-Gapped Interconnects, Self-Aligned Double Patterning and a 0.0588 um^2 SRAM Cell Size"   3. S. Im and K. Banerjee, "Full Chip Thermal Analysis of Planar (2-D) and Vertically Integrated (3-D) High Performance ICs"   4. C. Xu, K. Banerjee et al., "Compact Modeling and Analysis of Coupling Noise Induced by Through-Si-Vias in 3-D ICs"   5. H. Li and K. Banerjee, "High-Frequency Analysis of Carbon Nanotube Interconnects and Implications for On-Chip Inductor Design" - Lecture 15 - A Novel Variation-Aware Low-Power Keeper Architecture for Wide Fan-in Dynamic Gates   References:   1. H. F. Dadgour, K. Banerjee et al., "A Novel Variation-Aware Low-Power Keeper Architecture for Wide Fan-in Dynamic Gates"   2. H. F. Dadgour and K. Banerjee "A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic Or Gates" - Lecture 16 - Clocked Circuits, Timing and Clocking - Lecture 17 - Metal-Gate Work-Function Variability in Emerging Device Technologies   References:   1. H. F. Dadgour, K. Banerjee et al., "Grain-Orientation Induced Work-Function Variation in Nanoscale Metal-Gate Transistors -- Part I: Modeling, Analysis, and Experimental Validation"   2. H. F. Dadgour, K. Banerjee et al., "Grain-Orientation Induced Work-Function Variation in Nanoscale Metal-Gate Transistors -- Part II: Implications for Process, Device, and Circuit Design"   - Assignment 1   Due Date: Tue., May 23, at 4 pm   (To be collected by Junkai Jiang in class)   References:   1. Indranil De et al., “Impact of Super-Steep-Retrograde Channel Doping Profiles on the Performance of Scaled Devices,” IEEE Transactions on Electron Devices, vol. 46, no. 8, Aug. 1999.   2. R. H. Yan et al., “Scaling the Si MOSFET: From Bulk to SOI to Bulk,” IEEE Transactions on Electron Devices, vol. 39, no. 7, pp. 499-502, 1992. - TBA - Simulation software: (Manuals) - Circuit Netlist Simulator: HSpice - Analog Modeling: Verilog-A - Waveform viewer: CScope - Waveform viewer: AvanWaves - Circuit Layout Editor: MAX - Schematic Capture Program: SUE - Please do NOT print copies of these manuals! - For other tools, see Computer/Network Support - To set up the environment for your work,   see Environment Setup Guidance .

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