http://www.ece.ucsb.edu/courses/ECE225/225_W24Banerjee/ | http://tinyurl.com/2r3fpswv Course Info | Lecture Notes & Refs | Resources - ECE 225   High-Speed Digital Integrated Circuit Design   UCSB, ECE, Winter 2024 - Instructor: Prof. Kaustav Banerjee   kaustav (at) ece.ucsb.edu   Office: Harold Frank Hall (HFH) 4151   Phone: (805) 893-3337   Office Hour: Flexible, appointment by email. - Grader: Ankit Kumar   ankitkumar (at) ece.ucsb.edu   Office: HFH 2164   Office Hour: appointment by email. - Classroom: ESB 1003 - Schedule: Tue & Thu 4:00PM-5:50PM - For more info, please click HERE. -Assignment 1 - Due Feb 23rd 5:00 PM via GradeScope 90 nm PTM Model -Assignment 2 - Due Mar 8th 5:00 PM via GradeScope Final Project Report Format: [1] WORD [2] LATEX   Lecture 1 - Overview Reference(s):  1. G. E. Moore, "Cramming More Components onto Integrated Circuits"   2. P. Gelsinger, "Microprocessors for the New Millennium: hallenges, Opportunities, and New Frontiers"  3. S. Borkar, et. al, "Parameter Variations and Impact on Circuit and Microarchitecture"       Lecture 2 - Discussion of Project Topics       Lecture 3 - Review of CMOS Design       Lecture 4 - Review of Semiconductor Physics       Lecture 5 - MOSFET Scaling   References:  1. W. Cao, et al., "The Future Transistors," Nature, vol. 620, pp. 501-515, 2023.     Lecture 6 - Non-classical CMOS Devices   References(s):  1. R. H. Yan, et al, “Scaling the Si MOSFET: From Bulk to SOI to Bulk” IEEE Trans. Elec. Dev., vol. 39, no. 7, 1704-1710 (1992).  2. S. Rasouli, et al., "Design optimization of FinFET Domino logic considering the width quantization property". IEEE Trans. Elec. Dev., vol. 57, no. 11, 2934-2943 (2010).       Lecture 7 - Beyond CMOS Devices: TFETs References: 1. Y. Khatami and K. Banerjee, "Steep Subthreshold Slope n- and p-type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits," IEEE Transactions on Electron Devices, Vol. 56, No. 11, pp. 2752-2761, Nov. 2009. 2. W. Cao, et al. "Subthreshold-swing physics of tunnel field-effect transistors". In AIP Advances, Vol. 4, pp. 067141, 2014. 3. D. Sarkar, et al. "A subthermionic tunnel field-effect transistor with an atomically thin channel". Nature, Vol. 526, pp. 91-95, 2015. 4. W. Cao, et al. "Designing Band-to-Band Tunneling Field-Effect Transistors with 2D Semiconductors for Next Generation Low-Power VLSI". In IEEE International Electron Devices Meeting (IEEE, 2015). 5. W. Cao, et al. "Is Negative Capacitance FET a Steep-slope Logic Switch?". In Nature Communications, 11, 196, pp. 1-8, January 10, 2020.       Lecture 8 - VLSI Interconnects-I   References:  1. W. C. Elmore, "The Transient Response of Damped Linear Networks"  2. W. Nagen et al., "Interconnect-Power Dissipation in a Microprocessor"  3. Suaya, et al, "Modeling and Extraction of Nanometer Scale Interconnects: Challenges and Opportunities"       Lecture 9 - VLSI Interconnects-II   References:  1. A. Deutsch et al., "When are Transmission-Line Effects Important for On-Chip Interconnections?"  2. K. Banerjee and A. Mehrotra, "Analysis of On-Chip Inductance Effects for Distributed RLC Interconnects"  3. K. Banerjee, et. al., "Interconnect Modeling and Analysis in the Nanometer Era: Cu and Beyond"       Lecture 10 - Interconnect Design under Thermal, Power, Reliability, & Variability Constraints   References:  1. A. H. Ajami, et al., "Scaling Analysis of On-Chip Power Grid Voltage Variations in Nanometer Scale ULSI," Analog Integrated Circuits and Signal Processing volume 42, pages 277–290 (2005).  2. A. H. Ajami, et al., "Modeling and Analysis of Non-Uniform Substrate Temperature Effects on Global ULSI Interconnects," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, 6, 2005.  3. K. Banerjee et al., "A Power-Optimal Repeater Insertion Methodology for Global Interconnects in Nanometer Designs," IEEE TED, vol. 49, 11, 2002.  4. V. Wason and K. Banerjee, "A probabilistic framework for power-optimal repeater insertion in global interconnects under parameter variations" In Proceedings of the 2005 International Symposium on Low Power Electronics and Design, pp. 131-136, 2005.       Lecture 11 - Interconnect Design under Thermal & Reliability Constraints / Power Dissipation & Minimum Operation Voltage   References:   1. K. Banerjee and A. Mehrotra,"Global (Interconnect) Warming". In IEEE Circuits and Devices Magazine, vol. 17, no. 5, pp. 16-32, 2001.  2. S. Borkar, "Low power design challenges for the decade". In Proceedings of the ASP-DAC 2001, pp. 293-296, 2001.  3. T. Kuroda, "CMOS design challenges to power wall". In International Microprocesses and Nanotechnology Conference, pp. 6-7, 2001.  4. T. Sakurai, "Perspectives of Low-Power VLSI's". In IEICE Trans. Electron, vol. E87-C, 2004.       Lecture 12 -Nanoscale Power and Thermal Management: Self-consistent Thermal Profile Estimation      Design-Specific Metric Optimization   References:  1. S. C. Lin, et al., "A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs Part I: Electrothermal Couplings and Full-Chip Package Thermal Model". IEEE TED, vol. 54, 12, pp. 3342-3350, 2007.  2. S. C. Lin, et al., "A Self-Consistent Substrate Thermal Profile Estimation Technique for Nanoscale ICs—Part II: Implementation and Implications for Power Estimation and Thermal Management". IEEE TED, vol. 54, 12, pp. 3351-3360, 2007.  3. S. C. Lin, et al., "A Design-Specific and Thermally-Aware Methodology for Trading-Off Power and Performance in Leakage-Dominant CMOS Technologies". IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 16, 11, 2008.  4. S. C. Lin and K. Banerjee, "Cool Chips: Opportunities and Implications for Power and Thermal Management". IEEE Transactions on Electron Devices, vol. 55, 1, 2008.       Lecture 13 - BEOL Applications of Graphene in Next-Generation ICs   References:  1. C. Xu, et. al., "Modeling, Analysis, and Design of Graphene Nano-Ribbon Interconnects," IEEE TED, vol. 56, no. 8, pp. 1567-1578, 2009.  2. J. Jiang, et. al., "Intercalation Doped Multilayer-Graphene-Nanoribbons for Next-Generation Interconnects," Nano Letters, vol. 17, no. 3, pp. 1482-1488, 2017.  3. J. Jiang, et. al., "CMOS-Compatible Doped-Multilayer-Graphene Interconnects for Next-Generation VLSI," IEEE International Electron Devices Meeting (IEDM), pp. 34.5.1-34.5.4, 2018.  4. K. Agashiwala, et. al., "Demonstration of CMOS-Compatible Multi-Level Graphene Interconnects With Metal Vias," IEEE TED, vol. 68, no. 4, pp. 2083-2091, 2021.  5. J. Kang, et. al., "On-chip intercalated-graphene inductors for next-generation radio frequency electronics," Nature Electronics, vol. 1, no. 1, pp. 46-51, 2018.       Lecture 14 - 3D Integrated Circuits   References:  1. K. Banerjee et al., "3-D ICs: a novel chip design for improving deep-submicrometer interconnect performance and systems-on-chip integration". In Proceedings of IEEE, vol. 89, 5, pp. 602-633, 2001.  2. C. Xu et al., "Compact AC Modeling and Performance Analysis of Through-Silicon Vias in 3-D ICs". In IEEE TED, vol. 57, 12, pp. 3405-3417, 2010.  3. J. Jiang et al., "Ultimate Monolithic-3D Integration With 2D Materials: Rationale, Prospects, and Challenges". In IEEE Journal of the Electron Deivces Society, vol. 7, pp. 878-887, 2019.  4. D. Zhang et al., "0.5T0.5R—An Ultracompact RRAM Cell Uniquely Enabled by van der Waals Heterostructures". In IEEE TED, vol. 68, 4, pp. 2033-2040, 2021.       Lecture 15 - Memory   References: 1. R. W. Mann et al. "Ultralow-power SRAM technology". In IBM Journal of Research and Development, vol. 47, pp. 553-566, 2003. 2. J. A. Mandelman et al. "Challenges and future directions for the scaling of dynamic random-access memory (DRAM)" In IBM Journal of Research and Development, vol. 46, pp. 187-212, 2002. 3. J. Akerman "Toward a Universal Memory". In Science, vol. 308, pp. 508-510, 2005. 4. W. Cao et al. "Can 2D-Nanocrystals Extend the Lifetime of Floating-Gate Transistor Based Nonvolatile Memory?" In IEEE TED, vol. 61, pp. 3456-3464, 2014. 5. S. Raoux et al. "Phase change materials and phase change memory" In MRS Bulletin, vol. 39, pp. 703-710, 2014. 6. D. Zhang et al. "0.5T0.5R—An Ultracompact RRAM Cell Uniquely Enabled by van der Waals Heterostructures". In IEEE TED, vol. 68, 4, pp. 2033-2040, 2021.       Lecture 16 - Cryogenic 2D-CMOS Enabled Next-Generation High-Performance Large-Scale Quantum Computing   References:  1. K. Agashiwala, et. al., "Advancing High-Performance Large-Scale Quantum Computing using Cryogenic 2D-CMOS," IEEE International Electron Devices Meeting (IEDM), pp. 3.3.1-3.3.4, 2023.   Lecture 17 - Metal-Gate Work-Function Variability in Emerging Device Technologies   References:  1. H. F. Dadgour, et al., "Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part I: Modeling, Analysis, and Experimental Validation," IEEE TED, vol. 57, 10, pp. 2504-2514, 2010.  2. H. F. Dadgour et al., "Grain-Orientation Induced Work Function Variation in Nanoscale Metal-Gate Transistors—Part II: Implications for Process, Device, and Circuit Design," IEEE TED, vol. 57, 10, pp. 2515-2525, 2010.                                                                                                                         - Simulation software: (Manuals) - Circuit Netlist Simulator: HSpice - Analog Modeling: Verilog-A - Waveform viewer: CScope - Waveform viewer: AvanWaves - Circuit Layout Editor: MAX - Schematic Capture Program: SUE - Please do NOT print copies of these manuals! - For other tools, see Computer/Network Support - To set up the environment for your work,   see Environment Setup Guidance .   -Latest snippet to be added to .bashrc file  - ECE 122A - VLSI Principles, Fall 2023 - Nanoelectronics Research Lab

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Nanoelectronics Research Lab